What is bus bandwidth

[chetu]

Hello, I am studying computer science , and want to know what do you mean by the term bus bandwidth , i was studying about it yesterday but was confused and cound not understand , can you tell me what do you mean by bus bandwidth ,

For the FSB I think it is:
bus frequency * 4 (quad pumped) * 4 (4 transfers per cycle) * 16 (bits) / 8 (to convert to byte).
What makes for a FSB of 333: 333 * 4 * 4 * 16 / 8 = 10,656 GB / s
Could someone show me the calculation for the HT and the QPI also ?

please help

[MattyBoy]

Bus are a set of physical links (cables, printed circuit tracks, etc..) Can be exploited by different hardware components to communicate. The buses are intended to reduce the number of "pathways" needed to communicate the different components, from shared communications over a single channel of data. That is why the metaphor of "data highway" is sometimes used.

[Russell]

A bus is characterized by the volume of information that can be transmitted simultaneously. This volume, expressed in bits, is the number of physical lines on which data are sent simultaneously. A sheet of 32 lines can transmit 32 bits in parallel. It speaks of "breadth" to denote the number of bits that a bus can transmit simultaneously. On the other hand, the bus speed is also defined by its frequency (in Hertz), that is to say the number of data packets sent or received per second. It speaks of the cycle to identify each transmission or reception of data. In this way, it is possible to know the maximum bus speed (or maximum transfer rate), that is to say the amount of data it can carry per unit time, multiplying its width by its frequency .


also it is necessary for the FSB is to be of 64 bits (and quad pumped = 4 transfers per cycle)

Thus bus frequency * 4 (quad pumped) * 64 (bits) / 8 (to convert to byte). For the QPI and HyperTransport as implemented on Core i7 / Phenom the frequency of bus is * 2 (DDR) * 16 (bits) / 8 (to convert to byte) (each way)
(QPI frequency of 6.4 GT / s = 3.2 GHz)

[Joshua]

It is interesting to note that, to communicate, two buses were required to have the same width. This explains why of the RAM may need to be matched on some systems (eg on the first Pentium, including the processor bus width was 64 bits, it was necessary to install the memory strips of a width of 32 bits per pair).