Verilog HDL: What it is?

[Segvoia]

Hi, can anyone give the details about the Verilog HDL. In my college, one of the teacher is going to teach the Verilog HDL and before that we have given some assignments to complete. So, will you just help me in this case. I am expecting either details about it and also some reference book name or something. Please help me and reply me as soon as possible. I am waiting for your reply.

[opaper]

Hi, I don't know anything about the Verilog HDL, but when I searched on internet, I have got some verilog tools as follows. Just check whether it is helpful to you or not.

Simulators

• Verilog-XL : standard simulator in the market, this is the sign off simulator.
• NCVerilog : compiled simulator which works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL.
• VCS : This is worlds fastest simulator, this is also a compiled simulator like NCverilog.
• Finsim : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris.
• Aldec : This simulator from Aldec supports VHDL, Verilog, SystemC, SystemVerilog, PSL.
• Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog.
• Smash : mixed signal (spice), Verilog, VHDL simulator.
• Silos : Use to be fast and stable.
• Veritak : Verilog HDL Compiler/Simulator supporting major Verilog 2001 HDL features.
• MPSim : Axiom's MPSim is an integrated verification environment
• VeriLogger Extreme : High-performance compiled-code Verilog 2001 simulator.
• Zeemz : Verilog (IEEE 1364-2001) simulator and debugger

Free Simulators

• Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool.
• Verilator : Verilator is a compiled cycle-based simulator, which is free, but performs as fast as the commercial products.
• Cver : Cver is an interpreted Verilog simulator.
• Verilogger : The evaluation version is a free 1000 line free Verilog simulator plus an automatic test bench generation tool. Student versions start at $70 for 6 months.
• Veriwell : This is a very good simulator. Supports PLI and verilog 1995.

VCD Viewer

• nWave : One of the best VCD viewer, with support for large VCD dumps.
• Undertow : Undertow waveform viewer.
• GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers.
• Dinotrace : Freeware VCD viewer from veritools
• WaveViewer : SynaptiCAD's freeware VCD viewer also supports analog signal display and SPICE import.

Code Coverage

• Verification Navigator : An integrated design verification environment that enables a consistent, easy-to-use and efficient verification methodology with a powerful set of best-in-class tools for managing the HDL verification process.
• SureCov : Engineering teams designing today's chips and semiconductor IP cores need to know, with confidence, how thoroughly the functional test suite is exercising the design.
• Code Coverage Tool : A freeware code coverage tool.

Linting

• Leda : Leda is a code purification tool for designers using the Verilog® and VHDL Hardware Description Language (HDL).
• HDLint : A power full linting tool for VHDL and Verilog.
• nLint : nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system.
• SureLint : Designers need tools to analyze and debug their designs before integrating with the rest of the project.

Utils

• Teal : open source c++ class library for verification
• Jove : The Open Verification Environment for the Java (TM) Platform.
• FSMDesigner : FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way.
• TestBencher Pro : Generates bus-functional models and test benches from language independent timing diagrams.
• Timing Diagrammer Pro : A professional timing diagram editor with an unbeatable feature set.
• TimeGen : TimeGen is an engineering CAD tool which allows a digital design engineer the capability to quickly and effectively draw digital timing diagrams.
• WaveFormer Pro : Generates VHDL, Verilog, and SPICE code, and Patter Generator stimulus from timing diagrams.
• Timing Tool : TimingTool is a free to use on-line Timing Diagram Editor. This tool provides very good VHDL and Verilog test benches and requires no download or installation.
• Perlilog : Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs.

Source: asic-world.com

[MindSpace]

Hi, basically, Verilog HDL is come under the semiconductor and electronic design industry. Verilog is a hardware description language (HDL) used to model electronic systems. It is also used in the verification of analog and mixed-signal circuits.Verilog-95. It has some or the other versions such as Verilog 2001, Verilog 2005, SystemVerilog. For getting the reference of the Verilog HDL you can refer one of the following book:

• The complete Verilog book‎ by Vivek Sagdeo
• Verilog Quickstart: a practical guide to simulation and synthesis in Verilog‎
• by James M. Lee
• The Verilog PLI handbook: a user's guide and comprehensive reference on the verilog programming language interface by Stuart Sutherland
• Introduction to logic synthesis using Verilog HDL
• Verilog HDL: a guide to digital design and synthesis‎ by Samir Palnitkar

[Modifier]

Hi, verilog is a Hardware Description Language. You can get idea about how to use it with the help of following example:

A hello world program:

module main;
  initial 
    begin
      $display("Hello world!");
      $finish;
    end
endmodule

Example of two flip-flops :

module toplevel(clock,reset);
 input clock;
 input reset;
 
 reg flop1;
 reg flop2;
 
 always @ (posedge reset or posedge clock)
 if (reset)
   begin
     flop1 <= 0;
     flop2 <= 1;
   end
 else
   begin
     flop1 <= flop2;
     flop2 <= flop1;
   end
endmodule