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Hi all,
I heard that Verilog has integer type.
Someone said integer can be signed or unsigned.
How to declear signed integer?
And what's the difference with integer and reg signed [31:0](2's
complement) ?
Any suggestions will be appreciated!
Best regards,
You need [at least partial] 2001 support to use "reg signed". It isn't in the 1995 standard.
2) A variable declared integer is not necessarily exactly 32 bits wide. If I recall correctly, it must be at least 32 bits wide, but
it could be 64 bits wide if that were more convenient to the implementation.
3) In some implementations, I have found wierd artifacts occur when using integers in calculations that were longer that 32 bits wide,
they didn't necessarily sign extend in consistent ways past the 32 bit length, sometimes they would sign extend and other times that
would 0 pad.
4) You can't do bit-selects or part-selects on integers, just on regs (and wires, et al).
5) You shouldn't use "integer" declarations for things like flops or signals that will exist as actual circuitry (partially because of 2
through 4). You should use integer declarations only for for look indexes and similar items that "go away" as the design is turned
into silicon. You can use integers in non-synthesizable code, e.g. testbench parts.
Thus, if your tools are modern and support the current standard,you should use "reg signed" when you want a synthesizable part that
works in a signed way. If you don't have modern tools, life is more difficult.
I incorrectly said:
through 4). You should use integer declarations only for for look
I meant:
through 4). You should use integer declarations only for for loop
indexes and similar items that "go away" as the design is turned
Integers are always signed, and (usually, see Wingit comment) 32
bits wide.
Nothing, but it's often a convenience to have a signed value that is
not 32 bits wide.