Array in VHDL

Can i assign a std_logic vector to array of same bits?

suppose..

Code:

---

signal vec:std_logic_vector(15 downto 0);
type arr is array(o to 3) of std_logic_vector(0 to 3);
....
arr <= vec;

---

above mentioned code is right or wrong, if wrong is there any other way to assign std_logic_vector to array.

There are 3 errors in your code. Since vec is a 16-bit vector you cannot assign it to a 4-bit vector. When you assign a vector to an array of vectors you must specify an index. Also, you created the type arr, but did not declare a signal of that type. You can't make an assignment to a type. The following example may help.

Code:

---

type arr is array(0 to 3) of std_logic_vector(15 downto 0);

signal arr_a : arr;
signal vec_0, vec_1, vec_2, vec_3 : std_logic vector(15 downto 0);
....
arr_a(0) <= vec_0;
arr_a(1) <= vec_1;
....

---

I hope this helps.

I hve problem with generics and array in my code. Its like this,

Code:

---

generic (width:=16
--t_width :integer:= 8;
t_widths:=integer:=3;
t_size:= integer:=3);
signal ctrl:std_logic_vector(width-1 downto 0)
type ctrl_gen array(o to t_size)of std_logic_vector(0 to t_widths)

---

Now i need a logic to assign ctrl(vector) to ctrl_gen(array).

try this

Code:

---

arr(0)<= vec(15 downto 12);
arr(1)<= vec(11 downto ;
arr(2)<= vec(7 downto 4);
arr(0)<= vec(3 downto 0);

---

it is immpossible to assign vec directly to arr. you have to specify the address of arr and also break down the vector to 4 bits because your array is of 4 bits. Ok try this.

Here is another more generic way using a generate loop. If you were doing this in several places I would create a function to do it. Note I changed the indexing of the array elements to use "DOWNTO" instead of "TO".

Code:

---

CONSTANT VEC_WIDTH : integer := 16;
CONSTANT ARR_SIZE : integer := 4;
CONSTANT ARR_ELEM_WIDTH : integer := 4;
SIGNAL vec : std_logic_vector(VEC_WIDTH-1 DOWNTO 0);
TYPE arr IS ARRAY(0 TO ARR_SIZE-1) OF
std_logic_vector(ARR_ELEM_WIDTH-1 DOWNTO 0);
....
arr_assign_gen : FOR i IN 0 TO ARR_SIZE-1 GENERATE
arr(i) <= vec(i*ARR_ELEM_WIDTH-1 DOWNTO (i-1)*ARR_ELEM_WIDTH);
END GENERATE arr_assign_gen;

---

CONSTANT VEC_WIDTH : integer := 16;
CONSTANT ARR_SIZE : integer := 4;
CONSTANT ARR_ELEM_WIDTH : integer := 4;
SIGNAL vec : std_logic_vector(VEC_WIDTH-1 DOWNTO 0);
TYPE arr IS ARRAY(0 TO ARR_SIZE-1) OF
std_logic_vector(ARR_ELEM_WIDTH-1 DOWNTO 0);
....
arr_assign_gen : FOR i IN 0 TO ARR_SIZE-1 GENERATE
arr(i) <= vec(i*ARR_ELEM_WIDTH-1 DOWNTO (i-1)*ARR_ELEM_WIDTH);
END GENERATE arr_assign_gen;


In the above code, the assignment of signal vector to the array is not correct , i think. because, when i=0 then arr(0)<= vec(0 DOWNTO -4);
i=1 then arr(1)<= vec(3 DOWNTO 0);
so assignment should be as follows:
arr_assign_gen : FOR i IN ARR_SIZE-1 DOWNTO 0 GENERATE
arr(i) <= vec((i+1)*ARR_ELEM_WIDTH-1 DOWNTO i*ARR_ELEM_WIDTH);
END GENERATE arr_assign_gen;