Information about Programming for Multi-core processors

Hello everybody, I am new user to this forum. I have found some useful information about programming languages over here, so thought to register and post my doubt. Actually I was looking out for an information that will guide me to write some programs for multi-core processors. Let me admit that I am newbie for programs that are made for multi-core processors. So I was searching for some information that will explain the basic concepts of such programs. When I tried to search it on web, I found that there were many information but they didn't discussed about the concepts (those were for pro, maybe). So thought to post over here and get some simple concepts that I should be aware before trying these programs. More information you provide about this topic, would prove more kindness of yours. Please help me soon as possible. :notworthy

Hi,

You are right. Before knowing some basic concepts about the programming, it is useless just to write/note down the code. So i have tried to provide some basics of it. Multi-core processors enable parallel processing software and thus achieve higher performance. But the benefits of multi-core processors to place only when the software is optimized for CPUs. The performance of computer systems is growing steadily for years. This affects virtually all components of the computer. The most obvious is the performance gain in processors, memory and hard drives to pursue. But the graphics cards, network connections and other communication systems, such as USB or wireless connectivity reported rapidly increasing performance gains. The increasing performance of computers is leading to new applications and applications with comfortable user interfaces.

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The increasing performance of computers is leading to new applications and applications with comfortable user interfaces.

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These performance gains were mostly achieved in several ways:

• increase processing speed by faster clocking,
• a greater variety of functions,
• a shift of functions in the hardware,
• and increasing the capacity as in caches, memory or hard drives.

Most of these mentioned improvements also resulted in a higher power consumption of the IT modules. However, current flow generates heat, which is removed by cooling and again. This in turn increases the power consumption and thus operating costs. In order for the CPUs to reduce the power consumption, pursuing CPU manufacturers for several years, a different strategy and also orientate themselves in the techniques of parallel processing.

To carry the parallel processing, several techniques have been introduced, which should allow for parallelization of a sequential program. When parallel processing in this context all forms of parallel execution of code is understood. This includes the preliminary analysis of the instructions or loading from memory. The initial approaches to parallel processing subsumed in the techniques of the "Instruction Level Parallelism (ILP) with "Instruction pipelining", "Speculative Execution", "Out-of-order execution" or "Branch Prediction". It will seek to achieve through the parallel processing of instructions a time advantage. The "Instruction pipelining" about the code is passed through a pipeline and before the execution investigated Sun Matching instructions that can be run in parallel will need fewer cycles and total run time. In the out-of-order execution eventually leads to instructions in parallel from then whenever they do not have data dependency. The initiation of a variable for a loop could be so if it not already happened by the compiler or loader to be processed as out-of-order execution.

The "Speculative Execution" instructions are executed in the run-up already, even if not certain yet whether the instruction is actually needed. This applies whenever break branches or jumps, the linear program execution. In the "Branch Prediction" trying to jump the target at a code. Predictably, such as those at the instructions of a "if-else" or " switch case "occurs. This is based on analysis of previous commands, supported by a calculation of the probability for the subsequent code. If the branch destination in advance is known, the further execution of the code used on this earlier. "Branch Prediction" is usually used in conjunction with the "Speculative Execution". SIMD (Single Instruction, Multiple Data) enables parallel processing of data with equivalent structure. The SIMD concepts were originally applied in mainframes and supercomputers, and then found its way into the x86 architecture. SIMD allows simultaneous processing of parallel data streams. SIMD is used mainly in the processing of visual, audio and video data.

In addition to these procedures is the code optimization, which is achieved by sophisticated compiler techniques. In the following example that the first two operations are executed in parallel, which have no dependence (data dependency) to each other. In the parallelization of this code but must make absolutely sure, are that the third statement - the sum of education - is carried out only when the two partial sums are calculated.

Code:

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1. C = A + B
2. Z = X * Y
3. Sum = C + Z

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The goal of the compiler and CPU optimization is to identify possible parallelizable code sections to make this many and parallel to work. This is not easy, because the actual programming and almost all programming languages in use today and associated development tools are designed to sequential processes. The implementation of a sequential program into parallel pieces of code by the techniques of the "Instruction Level Parallelism" encouraged, but also their specific requirements. Modern CPUs are usually put together from several modules. These are the set of registers for temporary storage of data that Arithmetical and Logical Unit (ALU, calculator) to calculate the operations, and a decode logic for the commands.

To quickly get hold of data and instructions, are also cache (caches) are used. These are now always built in several stages and are usually referred to as first, second or third level cache. In general, the closer the cache on the CPU, the faster it can access it, but the smaller it is. In today's systems, the Level 1 caches are for about 32 Kbytes, Level 2 caches are enough to approach some MBytes and level-3 cache, more than 16 MB in size. In no case, however, the cache will ever reach the size of memory, which now extends to several gigabytes. The cache is used, as mentioned, only the faster access to required data and instructions. On branching, ie, the continuation of the code elsewhere, provide speculative execution and branch prediction for the cache to be filled in time with the required content. The management of caches is performed by the CPU and runs silently by the program code. However, should a software developer on the existence and operation of the cache must be clear, as many branches or jumps in the code lead inevitably to many cache operations to itself. Also to be considered in parallel access to data, the contents of the cache.