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Thread: Linux Makefile

  1. #1
    Join Date
    Sep 2010
    Posts
    66

    Linux Makefile

    The make command knows how to make some files for example, it will create foo from foo.c or toto.cc. In these cases, a Makefile is not even necessary. However, most of the time, we need a Makefile: either to indicate the dependencies between different files, or because the commands to start the compilation are not very standard. Here's an example Makefile. The first line contains the name of "goal" followed by a colon. The following lines (which must begin with a tab --- make is really archaic software) contain commands to start to achieve that goal. To launch the compilation, one would type make or make all (the name all nothing special: it's just the first goal that appears in the file).
    Code:
    all:
             latex 1
             dvips-E-o 1.ps 1.dvi
    It may indicate the dependency between the different files: In the following example, we want to get a file 1.ps, which comes from a file 1.dvi who comes from a file 1.tex. The make command will compare the dates of last modification of these files (if they exist) and thus judge whether it is necessary to recreate some or all of these files.
    Code:
    all: 1.ps
    
     1.ps: 1.dvi
             dvips-E-o 1.ps 1.dvi
    
     1.dvi: 1.tex
             latex 1

  2. #2
    Join Date
    Sep 2010
    Posts
    66

    Re: Linux Makefile

    Orders must be on one line. If you need more lines, we will put a backslash at the end. (Find a good example ...)
    Code:
    all:
             trial.tex latex, bibtex trial; trial.tex latex, latex trial.tex; dvips-o trial.ps trial.dvi
    Code:
    all:
             Latex trial.tex; \
             bibtex trial; \
             Latex trial.tex; \
             Latex trial.tex; \
             dvips-o trial.ps trial.dvi
    Because the $ character is interpreted by make, we must double if we want it to be by the shell. (We see later comments cleaner rewrite this example.)
    Code:
    all:
             Latex trial.tex
             bibtex trial
             Latex trial.tex
             Latex trial.tex
             dvips-o trial.ps trial.dvi

  3. #3
    Join Date
    Sep 2010
    Posts
    66

    Re: Linux Makefile

    Using variables

    It defines and uses a variable like that. do not forget the parentheses.
    Code:
    TEX = 1.tex 
     LATEX = latex-interaction = nonstopmode-shell-escape
    
     all: 
             $ (LATEX) $ (TEX)
    You can use a variable in the definition of another variable.
    Code:
    MORE = A.tex B.tex
     TEX = 1.tex 2.tex 3.tex 4.tex $ (MORE
    The following example is equivalent (but do not copy provided).
    Code:
    TEX = 1.tex 2.tex 3.tex 4.tex $ (MORE)
     MORE = A.tex B.tex
    When make knows how to create a file from another without being told (eg, a *. o file from a *. c), we can still control its behavior using some variables.
    Code:
    CC = gcc
     CXX = g + +
     CPP = $ (CC)-E
     CFLAGS =-Wall-O2 -I/usr/X11R6/include 
     CXXFLAGS = 
     LDFLAGS =

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