Changes of AMD K10 Microarchitecture

[Jigisha]

Can anyone explain me changes in AMD K10 Microarchitecture? I hope that most of you might have heard about this. There are needs to be a simple explanation regarding this and i am looking forward for it.

[brynhildur]

I'm especially curious on AMD's top models of the K10, even if they are for now still be coming. Should not be superior to the Conroe, I was already know about the flop, because you should not forget Intel's Penrym. AMD should get the problem of high frequencies then still in its grip, but I see no big problems.

[Valdis]

The integrated memory interface, the showpiece of the K8 architecture, has been with the K10 architecture, improved and extended sense, although AMD anticipates that in the server space to support up to DDR2 667th It is unclear how it looks on the desktop CPUs. DDR2 800, there should be at least, rumors even speak of DDR2 1066th But it definitely will not initially be DDR3. It wants to be preserved for the first update of the core, which is according to the current state of knowledge in the second quarter of 2008.

[HALLBJORN]

With the introduction of the AMD K10 microarchitecture in November 2007, the end of the K8 and K9-era is heralded. The K10-generation, which is from the ground up as a multi-core processor is based on long been used AMD64 micro-architecture. On the first family member, the Phenom X4 were housed four cores. Each core can gain exclusive access to its own 128 KB of L1 cache, L2 cache and 512 KB large. The Phenom has a dual-channel DDR2 memory controller supports DDR2 SDRAM at 1066MHz. One of the most important innovation is but one shared by all cores 2 Mbyte L3 cache.

[Eyvindur]

The improvements include the increase of the memory interface of the memory bank to support second Similarly, the memory buffer has been increased and optimized for DDR2 memory. Furthermore - Core microarchitecture can greet - a prefetch algorithm has been integrated. This means that the CPU is trying to identify a logical method by which data is requested from memory. Ideally, the processor would know what data is needed next, and could send it to the memory in advance. Means of a further update of the prefetcher unit can now be loaded at the data in the L1 cache without having to take the detour via the L2 cache. How is this optimization has a positive effect on performance is difficult to assess, because the Core microarchitecture are not familiar with this feature.

[Jokull]

Launch of the second Generation processors with K10 micro-architecture. The first Phenom II processors have been temporarily plugged into the socket AM2 +, with the consequence that they had to work with DDR2 SDRAM. K10 processors from the second However, the next generation have dual-channel DDR2 memory controller and a faster dual-channel memory controllers for DDR3 SDRAM. Therefore, Phenom II, Athlon, Opteron and Athlon II processors, with the introduction of Socket AM3 February 2009 on these calculated their store data in memory.

[Ryder Allen]

Ideally, AMD over Intel can save four times the cache through the shared L3 cache, because all four cores can access the same data. But for Intel, the L3 cache is nothing new, then it was taken one for the Extreme Editions Pentium 4. Intel wants to retrieve the L3 cache with the new for 2008 announced Nehalem architecture - it will be interesting.

[Jailekhaa]

One of the major issues before proceeding with the sale of the first K10 processors is that the clock frequency. Actually, it was assumed that Barcelona (server) and Agena (desktop) clock speeds to withstand up to 2.9 GHz would. First unofficial roadmaps corroborated these rumors also flawless. Definitely improved the Pro / MHz performance in the neck - the factor by which was only sometimes unclear - they figured out that the K10 would at least catch up to Intel. Opinions as "at least has the K10 architecture, the Core microarchitecture, a year ahead," confirmed the assumption that K10 is superior to the highly acclaimed Core microarchitecture.

[Usha Kiran]

AMD is going back to his strength with which you could score a few years ago fully: the energy consumption. AMD announces joyfully that the quad-core series, the loss of power classes 68 -, 95 - and 120 watts will give. So AMD would have quietly increased the number of cores from 2 to 4, without giving rise to the energy needs there.

[Victorious mind]

The ninth generation of x86 processors, the AMD K10 microarchitecture (K9 was never officially released and skipped the part of AMD). Although already released the first Opteron-based processors in the server segment in September 2007 on the K10 micro-architecture, this was later known to properly launch the Phenom X3/X4 processors.

[Muwafaq]

AMD provides customers with an impressive quad-core technology. Whether one accepts the revised memory interface that is at all corners and edges have been optimized, or to the L3 cache, which can save in the ideal case, four times the cache compared to Intel, fished out: AMD seems designed to have and at the right points hand the former K7 architecture - it is still more "Athlon XP" in the K10 architecture than you think - have to be overhauled significantly. One lot has been copied from the Core microarchitecture and also assumed, however, also realized a lot of their own ideas about which one but unfortunately does not yet know what effect they have in practice.