Originally Posted by
Gimbya
CAS Latency (also labeled as the CAS latency, CAS Timing Delay) the number of clock cycles that pass from the column that addressed the data arriving at the checkout. The memory manufacturer lists the best possible configuration in CL qualification.
Command Rate (Rates are also labeled as CMD) the number of clock cycles needed to cope with the memory modules and memory chip with the data of the desired area. If the memory banks are filled to capacity, will have to increase this rate to two, resulting in a significant decrease in performance.
Reply 5
Bookmarks