Intel Core 2 Extreme QX9650

[The$Hulk]

I would like to discuss some information about the Intel Core 2 Extreme QX9650.

The Core 2 Extreme QX9650 is based on the Penryn microarchitecture. This is an evolution of the Core microarchitecture (NGMA, Merom micro-architecture). In the context of the Tick-Tock model is a "tick" that serve as pioneers of a new manufacturing technology (45 nm) and contain little expensive improvements to an existing architecture. Although the new products are faster to 45 percent - more on that later - take this not as an opportunity to already "Core 3" set as the product name. The supported instruction sets for the first time include the Streaming SIMD Extensions (SSE) version 4.1. No difference in the control of the processor with a system clock of 333 MHz, which as usual means a quad-pumped bus of 1333 MHz. As with the other editions of Extreme Intel QX9650 is the new open at the top of the multiplier. By default, it is, however, 9 and thus generates the normal state in the 3.0 GHz clock frequency. To change the multiplier and the set front-side bus will come later in the "overclocking" to speak. Originally, the audit planning a rhythm of A0 - instead of the revision C0 and A1 ->> B0 - before, of which B1> latter worked the final revision should be. In the course of the last few months we decided against the B1 revision, however, . Where: A modification of the letters are not only the metal layers, but also the layers of silicon-created. to change only the number, the silicon remains unchanged.

Expecting that other members will post more information.

[Lawford]

The Penryn microarchitecture is used in mobile, desktop, workstation (DP) and server (MP). Its area of operations according to some of these cars have special functions. In such a case is explicitly mentioned. As a close relative of the Core microarchitecture is to inherited characteristics compared to Pentium 4 and Athlon 64 is not discussed separately. For a basic understanding of core and the instruction execution in an out-of-order pipeline as a consideration of the following image gallery is recommended. But now to the Penryn-family: According to current knowledge models are two to six processing cores planned to carry the following code names.

• Mobile: Penryn (Dual Core)? (Quad Core, two Penryn chips)
• Desktop: Wolfdale (Dual Core), Yorkfield (quad core, two Penryn chips)
• Workstation: Wolfdale-DP (Dual Core), Woodcrest (Quad core, two Penryn chips)
• Server: Dunnington (6-core, a chip, unsecured rumored)

The improvements of Penryn are concentrated in the areas of out-of-order execution, cache / memory and power management. In the area of execution, the previous radix-4 replaced by a Radix-16-Dividierer/Quadratwurzeleinheit. Also accelerates the new Super Shuffle Engine SSE instructions that have to do with the bit manipulation. In addition, supported the three existing SSE units now SSE4. In the area of cache / memory, the store forwarding improved and the associativity of the L2 cache. Power management was completed by a C6-state (Deep Power Down) and improved Dynamic Acceleration Technology (EDAT).

[TechPredator]

To accelerate multimedia applications waiting on Penryn with SSE4.1. This expansion includes 47 new SIMD instructions that cover a variety of areas. Although covering various areas of the new commands, Intel looks really only one area in the SSE4 can provide a massive boost in speed: Video Coding. More generally, all the algorithms that must perform a Motion Estimation - Games generally do not belong in it. As a first application since version 6.6.1 DivX support the new commands. Depending on the setting to see Intel's testing revealed the speed advantage of up to 63 percent. More SSE4 applications are already on the horizon: the beginning of November expected TMPGenc Xpress 4.4 Encourage them to be and should experience a performance increase of 40 percent. Adobe Premiere CS3 for a patch in development, to be published the end of 2007 and a speedup of up to 38 percent are performed. Even Adobe Photoshop CS3 will be equipped with an update for the new commands. This seems likely but not in the next six months.

[Gefry]

The Memory Order Buffer (MOB) can store and manage operations on unaligned addresses is now better. In the program flow, it happens very often that an address in memory first data is written to be read and a short time later. Since memory accesses are associated with high latency and memory bandwidth is also limited, attempts to avoid unnecessary requests. Ideally, a store instruction reaches its result directly to a later address to the same place more load. This process is known as a store-forwarding and the MOB performed. Compared to the Merom MOB this process can now also perform poorly placed in operations more frequently, which is the effective bandwidth to the best. Originally, also for Penryn "Split Load Cache Enhancements planned, with the help of those two separate requests to the cache would have been possible. This is always an advantage when accessing data (L1 data cache) that are not properly aligned to addresses. Overlaps a data entry (less than 128 bits), two cache lines, so for this purpose are currently two separate requests necessary. Penryn would divide a 128-bit access - can load and so on "happy unaligned" data in a bar, the complete set of information in the working registers - probably in two 64-bit accesses. In the recent presentations of this feature is not more talk. A statement from the press office is still pending. Especially for the upcoming notebook processors of the Penryn generation, Intel has two innovations in the pipeline. The new Deep Power Down Technology (C6) switches in idle state from almost the entire processor helps so much to save power.

[Mentos]

Due to the lengthy procedure and the voltage adjustment C6 makes sense only if the processor can sleep at least 4-5 ms, before being woken by the chipset (eg timer interrupt, keyboard interrupt, etc.). With open Windows Media Player Windows will automatically increase the interrupt Frequenter of 16 to 1 ms. This C6 in this case is not detrimental to (the operating system does not explicitly C6), a memory has been implemented. C6 has not paid off the last time, demote car enters into force and the requirement of the operating system, for example, with C4 override. The feature will remain exclusive to the notebook-processors. The frequency of these processors is not chosen by what is technically possible, but what of the thermal design power (TDP), so the power consumption is provided. This mobile chips have a certain clock game room that is used in desktop processors from the start. Available for servers importance but for all products, Penryn will also score in virtual machines. With the help of state management VMCs caching can be commands to enter and leave a virtual machine runs much faster, as safety questions can be optionally retrieved from the state cache. The process of changing (task switch) to virtual machines should be able to be carried out faster by 25 to 75 percent.

[Umberto-Micro]

The problem with servers: It must be ensured data consistency. This is achieved by snooping (snooping). Here, listen to all the cores to the memory buses and intervene if their cache is a date that is newer than that in the memory (or has been marked as exclusive, MESI protocol). L1 cache snooping is priced at idle processor power is unnecessary and easily avoided if individual cores in the C3 (CC3 hence the name) change. The CC3-state of the L1 cache is emptied and turned off (sleep transistors). As a side effect of L1 cache snooping for this core is prevented. The power consumption can be reduced by up to 16 percent hereby.

[Alondra]

With Intel may P1266 without expensive re-equipment of Fabs, ie using existing tools and the use of light sources with 193-nm wavelength, double the transistor density or reduce the chip area but the processors and thus increase the numbers dramatically. The time required for a switching operation of energy - as in CMOS circuit technology is, because of the complementary working N-and P-channel transistors exclusively with the state change (eg from 0 to 1) a current - could be reduced by 30 percent. The switching speed could be increased by 20 percent. This climbs the possible clock frequency of the entire circuit up. Similarly, with this improvement, without turning on the clock, undesirable parasitic currents from source to drain can (both terminals of the "switch") can be lowered by a factor of five. The 20 percent higher switching speed can not be changed at will against a factor of 5 reduced leakage current (Ioff). Rather, it is this is a paramater (Threshold voltage) that is set in processor production. The choice of this voltage to move shows to a straight line to the relationship between transistor speed and leakage currents (see picture). The 45-nm production of Desktop-/Server-Processor were designed for speed on the notebook processors save power.

[DarenHawk]

The main innovation and the reason for the lower leakage currents and higher performance of P1266 is the use of a new gate material and a new gate insulator. At the gate oxide Intel relies on an unspecified hafnium-based material on the disabled compared to last only 1.2 nm thick silicon oxide (5 atomic layers), the tunneling of the electrons much more effectively. In the first research publications from November 2003, worked with a thickness of 3.0 nm. Since then, Intel has provided no new information. What is clear is that it is thicker than 1.2 nm and thus the leakage current greatly reduced without affecting the transistor performance. For the speed of a transistor is the oxide capacitance a crucial variable. It indicates how many carriers are at a gate voltage applied in the channel for a current commercial operators. At a constant dielectric constant, the oxide thickness is less in favor of faster transistors, however. For the thinner, the higher the oxide capacitance and thus the opposite inversion capacitance in the channel between source and drain. The greater this capacity, the greater the current that can flow through the transistor and the faster it can switch (connected to it Gates). The currently used silicon dioxide has a dielectric constant of 3.9. The value of the new material is not known, however, Intel has given readings for 2002, some the size of the oxide capacitance known.