Rambus, a developer of high-speed interfaces and memory technologies, on Monday announced its Mobile Memory Initiative. This development effort focuses on high-bandwidth, low-power memory technologies targeted at achieving data rates of 4.3GHz at best-in-class power efficiency.
At 4.30GHz clock-speed, a 32-bit memory device can provide 17.2GB/s peak bandwidth; provided that Rambus wants to make such devices extremely effective in terms of power consumption, the memory technology may find itself inside powerful mobile multimedia-oriented devices, such as portable video game consoles, smartphones and so on.
Rambus has combined its high-bandwidth expertise with power-efficient signaling technology to create key innovations for its Mobile Memory Initiative, such as:
- Very Low-Swing Differential Signaling - combines the robust signaling qualities of a differential architecture with innovative circuit techniques to greatly reduce active power consumption;
- FlexClocking™ Architecture - a clock-forwarded and clock-distributed topology, enables high-speed operation and a simplified DRAM interface;
- Advanced Power State Management - in conjunction with the FlexClocking architecture, provides fast switching times between power-saving modes and delivers optimized power efficiency across a diverse range of usage profiles.
Building on innovations pioneered through the development of the award-winning XDR memory architecture, and through the Low-Power and Terabyte Bandwidth Initiatives, Rambus’ Mobile Memory Initiative also incorporates key innovations such as FlexPhase and Microthreading technology.
Rambus will demonstrate a silicon test vehicle for its Mobile Memory Initiative at DesignCon 2009.
Source: XbitLabs
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