How are caches updated on write?

[Aasha]

I am having a small query related to the Cache update. I am aware that it the processor is wants to store the value then it takes the memory on cache and some on the RAM but this is for the L1. I wanted to whether this is possible only for the L1 or L2, L3 will also go through the same. If any one is having the knowledge about the same then please let me know. Thanks in advance.

[Eric B]

I have gone through the same and let me tell you that Both exclusive and inclusive caches are used. The L1, L2 and L3 all are using the same method for the saving of the memory that you are talking about. So if you are thinking about and let me know whether you are getting it work or not.

[chroma]

To improve the execution speed of programs, some CPUs are 68 000 family can "hide" the memory accesses. Caches are always called using logical addresses, including the functional code of access. This means that accesses the user mode or supervisor different entries in the cache. I hope this will help you with the same.

[Macarenas]

By default, the areas used by WHDLoad, Slavic expansion and memory are marked as cacheable, Copyback. The base memory (chip) is marked as non-cacheable, and data and instruction caches are enabled in the CRTA. Thus, the program located in the area of base memory cache but runs without WHDLoad slave and use caches for optimal performance.

[Sam.D]

If the programmer has worked well, then the user has nothing to do about the cache because the settings are already made in the slave. However, there may be two reasons for changing manual settings cache. First to run an install that does not work well because it is running too fast (e.g. Graphical errors) and then to run a program installed quickly. To run a program that crashes, the option NoCache can be used. This option disables all caches and mark all the memory as non-cacheable serialized (precise). If the machine has the memory chip 32-bit, it will remain faster than on a basic A500.

[ThoMas321]

The connection cache is only available on the 68060. It's kind of hide instructions for branch instructions. But the difference with the instruction cache is that it is not affected by the settings MMU! This means that even if the page is marked as non-cacheable, the branch instructions will be cached if the cache connection is enabled.

[blindsleeper]

The cache can be addressed not only by the processor itself (CRTA) and MMU settings, but also by external hardware. The processor signals on the bus when he tries to hide access. Similarly, an external device can send a signal to the processor (after an address has been placed on the address bus during memory access) requesting that an access is not hidden.

[monsitj]

The mechanism that signals the processor that the memory is cache or not is (from what I know) used on all and CPU boards that contain a CPU 68030 or higher (because they have a data cache). The affected areas are the entire memory chip and the memory input-output which should not be hidden by the data cache. This is necessary to avoid inconsistencies, for example due to DMA mechanisms.