VHDL 16-bit barrelshifter Question

[Stefan09]

Hello guys , I am newbie in VHDL.I want to program a 16 bit barrel shifter with the following specifactions:

shifts left, inserts zeros on the right -- realized with command sll
S is a 4 bit input signal that dictates the amount of places the 16 bit signal needs to shift.

I had this following code but that doesn't work thanks to the command integer(S) and sll. I tried all kinds of loops, but my java experience is probably making me do all kinds of weird things with the syntax. Please help me out!

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity b16 IS
PORT (
    DIN: in STD_LOGIC_VECTOR(15 downto 0); -- input
    S: in STD_LOGIC_VECTOR (3 downto 0); -- Shift amount, 0-15
    DOUT: out STD_LOGIC_VECTOR(15 downto 0) -- output
);
END b16;


architecture b16_arch of b16 is
    FUNCTION shift (DIN:std_logic_vector; S:std_logic_vector) RETURN std_logic_
vector IS
    VARIABLE x : std_logic_vector(15 downto 0);
      BEGIN
      x := DIN;  
      x sll integer(S);
      RETURN x;
    END shift;
    BEGIN
      DOUT <=conv(DIN,S);
END b16_arch;

Thanks & regards

[JoeFrat]

as a newbie i think so you need to assign the value back to x,not really sure about this . like x:= x sll integer(S); just try it...

[Stefan09]

I got this error message

# ** Error: 16bitshift.vhd(17): Illegal type conversion from std_logic_vector to integer (array to numeric).
# ** Error: 16bitshift.vhd(19): No feasible entries for infix operator "sll".
# ** Error: 16bitshift.vhd(19): Bad right hand side (infix expression) in variable assignment.
# ** Error: 16bitshift.vhd(23): Unknown identifier 'conv'.
# ** Error: 16bitshift.vhd(24): VHDL Compiler exiting

while executing this code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity b16 IS
PORT (
	DIN: in STD_LOGIC_VECTOR(15 downto 0); -- input
	S: in STD_LOGIC_VECTOR (3 downto 0); -- Shift amount, 0-15
	DOUT: out STD_LOGIC_VECTOR(15 downto 0) -- output
);
END b16;


architecture b16_arch of b16 is
	FUNCTION shift (DIN:std_logic_vector; S:std_logic_vector) RETURN std_logic_vector IS
	VARIABLE x : std_logic_vector(15 downto 0);
	VARIABLE y : integer range 0 to 15;
	  BEGIN
	  y := integer(S);    
	  x := DIN;  
	  x := x sll y;
	  RETURN x;
	END shift;
	BEGIN
	  DOUT <=conv(DIN,S);
END b16_arch;

So, i got two question for you
1. How do I convert S into an integer?
2. How do I use the operand sll properly? Doing a loop with sll in it S times? Or can I do x sll 5 for example? and how do I get the result into the variable?

thanks for your reply

[JoeFrat]

I got this error message

# ** Error: 16bitshift.vhd(17): Illegal type conversion from std_logic_vector to integer (array to numeric).
# ** Error: 16bitshift.vhd(19): No feasible entries for infix operator "sll".
# ** Error: 16bitshift.vhd(19): Bad right hand side (infix expression) in variable assignment.
# ** Error: 16bitshift.vhd(23): Unknown identifier 'conv'.
# ** Error: 16bitshift.vhd(24): VHDL Compiler exiting

while executing this code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity b16 IS
PORT (
	DIN: in STD_LOGIC_VECTOR(15 downto 0); -- input
	S: in STD_LOGIC_VECTOR (3 downto 0); -- Shift amount, 0-15
	DOUT: out STD_LOGIC_VECTOR(15 downto 0) -- output
);
END b16;


architecture b16_arch of b16 is
	FUNCTION shift (DIN:std_logic_vector; S:std_logic_vector) RETURN std_logic_vector IS
	VARIABLE x : std_logic_vector(15 downto 0);
	VARIABLE y : integer range 0 to 15;
	  BEGIN
	  y := integer(S);    
	  x := DIN;  
	  x := x sll y;
	  RETURN x;
	END shift;
	BEGIN
	  DOUT <=conv(DIN,S);
END b16_arch;

So, i got two question for you
1. How do I convert S into an integer?
2. How do I use the operand sll properly? Doing a loop with sll in it S times? Or can I do x sll 5 for example? and how do I get the result into the variable?

thanks for your reply

You can try the following. Hope this is what you want. You may like to add handshaking and clock signals so the system knows when to start listening to the next "s" signal. Or if there is just one constant "shift-by-amount", you can use "s" as an internal signal rather than an input.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity b16 is port(din: in std_logic_vector(15 downto 0); -- input
	s: in std_logic_vector(3 downto 0); -- Shift amount, 0-15
	dout: out std_logic_vector(15 downto 0));
end b16;

architecture b16_arch of b16 is
	function shift (din:std_logic_vector; s:std_logic_vector) return std_logic_vector is
	variable x:unsigned(15 downto 0);
	variable y:integer range 0 to 15;
	begin
		y:=to_integer(unsigned(s));    
		x:=unsigned(din);
		x:=x sll y;
		return std_logic_vector(x);
	end shift;
begin
	dout<=shift(din,s);
end b16_arch;