TechArena Community program card counter on FPGA

#1
22-12-2008
 Member Join Date: Nov 2008 Posts: 23
program card counter on FPGA

I have already set a meter from 00 to 99 on a map FPGA, (Basys100 Spartan3e - Tq144), I use Xilinx. whenever the switch (Load) is active, the counter account 00,01,02,03,04 ... up to 99. I would like to know if there is a way to a reversal. When I turn a switch, I want the code to make a "decrement" ... if the meter is, for example, is a 00, when I activate the switch, the account must show 99 ... the Similarly, if the meter is in the process of increment 55,56,57 ... and I activate the switch, it must resume 57 and decreases 56,55,54 ... ideas?

Thank you
#2
22-12-2008
 Member Join Date: Oct 2005 Posts: 2,389
Re: program card counter on FPGA

Hi,

My experience in VHDL is a bit ... But I think it would be easier to help you if we put a little piece of your code here.

And if not, if you do something like

Code:
``` meter entity is
port (
switch: in std_logic;
output: out unsigned (6 downto 0)
)
end entity```
and the architecture of the meter, if you add a

Code:
```if switch ='0 'then
output <= output + 1;
else
output <= output - 1;
end if```
#3
22-12-2008
 Member Join Date: Nov 2008 Posts: 23
Re: program card counter on FPGA

it's good thank you I managed to do so

Code:
``` process (count, invert)
begin

if invert ='1 'then
case count is
when "0000" => ASG <= "00001001";
when "0001" => ASG <= "00000001";
when "0010" => ASG <= "00011111";
when "0011" => ASG <= "01000001";
when "0100" => ASG <= "01001001";
when "0101" => ASG <= "10011001";
when "0110" => ASG <= "00001101";
when "0111" => ASG <= "00100101";
when "1000" => ASG <= "10011111";
when others => ASG <= "00000011";
end case;

else
case count is
when "0000" => ASG <= "00000011";
when "0001" => ASG <= "10011111";
when "0010" => ASG <= "00100101";
when "0011" => ASG <= "00001101";
when "0100" => ASG <= "10011001";
when "0101" => ASG <= "01001001";
when "0110" => ASG <= "01000001";
when "0111" => ASG <= "00011111";
when "1000" => ASG <= "00000001";
when others => ASG <= "00001001";
end case;
end if;
end process;```
#4
22-12-2008
 Member Join Date: Nov 2008 Posts: 23
Re: program card counter on FPGA

Otherwise I can not program a binary converter a BCD, ie, a converter that accepts 8-bit (8-bit input) and displays on the 7-segment display the corresponding number, do you think you could help me?

this code displays the same number from 0 to 9 within 4 meters at the same time. I do not know how to isolate the units and tens.

Code:
``` LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY IS BCD2LED

PORT (D: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
SSG: OUT STD_LOGIC_VECTOR (6 DOWNTO 0));

END BCD2LED;

RTL OF ARCHITECTURE IS BCD2LED
BEGIN
PROCESS (D)
BEGIN
CASE IS D - GFEDCBA - (1: OFF - 0: ON)
WHEN "0000" => ASG <= "1000000"; - 0
WHEN "0001" => ASG <= "1111001" - 1
WHEN "0010" => ASG <= "0100100" - 2
WHEN "0011" => ASG <= "0110000"; - 3
WHEN "0100" => ASG <= "0011001" - 4
WHEN "0101" => ASG <= "0010010"; - 5
WHEN "0110" => ASG <= "0000010"; - 6
WHEN "0111" => ASG <= "1111000"; - 7
WHEN "1000" => ASG <= "0000000"; - 8
WHEN "1001" => ASG <= "0010000"; - 9

WHEN OTHERS => ASG <= "1000000";
END CASE;

END PROCESS;

END RTL;```
#5
22-12-2008
 Member Join Date: Oct 2005 Posts: 2,389
Re: program card counter on FPGA

It seems to me that this be managed at the time you set mapping input / output of your FPGA with Xilinx. It is not in the code that it happens.

EDIT:

here, I found an explanation

http://www.derepas.com/fabrice/hard/

but apparently you have 4 outputs' D14 ',' E14 ',' F14 'and' G14 'which define what you want to display your value. You have Mettes'1 'on the display you want and you force others to'0'.

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