Basic VHDL Questions

[Keegan]

Can anybody tell me what is the difference in simulation and synthesis by putting what I call assignments inside processes? The only thing I can tell is that in ModelSim, the workspace list will have a process name label on the assignment rather than a line__xx label.

a <= b and c;

or

a_process(b,c)
begin
a <= b and c;
end process;

pls helps

[DAIJIRO]

One simulation difference is that signals in a process all get updated at the end of the process..So

a <= b and c; -- #1
d <= e and f; -- #2

You have no 'control' over whether #1 or #2 gets evaluated first so there may be a simulation delta time between when signals 'a' and 'd' change. If you have the same statements within a process (with the appropriate sensitivity list of course) then 'a' and 'd' will always change at the exact same time on the same simulation delta time as well.It's very rare where this subtle difference makes any difference at all. I've never needed it when writing code that needs to be synthesizable, I have in a couple instances used this when writing non-synthesizable simulation models. unfortunately the situation where it was useful escapes me just now but since you're asking a 'basic VHDL question' my guess is that you won't run across a need for this for a while if ever. From a synthesis perspective it makes no difference, both ways will produce the same result.From a practical standpoint, just putting the equations without a process is somewhat cleaner since you don't have to check (and recheck) that you have all the appropriate signals in the sensitivity list. For example, look at the following code. If you run with a proper simulator, signal 'd' will not get updated when signal 'e' and 'f' change...unless they happen to be coincident with signals 'b' and 'c' changing since only 'b' and 'c' are in the sensitivity list so the process only gets executed when there is a change to either 'b' or 'c'.

a_procrocess(b,c)
begin
a <= b and c; -- #1
d <= e and f; -- #2
end process;

If you take this code and synthesize it, your synthesis tool will probably kick out a warning about an incomplete sensitivity list and implement what you had probably had intended all along (i.e. 'd' will get updated when either 'e' or 'f' change. Although that is probably what you had intended it does mean that what gets compiled into your physical device will not be the same thing that you're seeing in simulation. From my perspective having simulation not matching reality is a bad thing. As a general guideline I personally tend to avoid processes other than clocked processes for just this reason....much less chance for mucking up something since of course 'real' code will not be quite so easy to spot that signals are missing from the sensitivity list.

[Conrad]

Can anybody tell me what is the difference in simulation and synthesis by putting what I call assignments inside processes? The only thing I can tell is that in ModelSim, the workspace list will have a process name label on the assignment rather than a line__xx label.

a <= b and c;

or

a_process(b,c)
begin
a <= b and c;
end process;

pls helps

Those two chunks of code are identical by definition in VHDL. As you say, ModelSim and other simulators may give you slightly different views of them, and may optimize them in slightly different ways, but it is mandatory that they give identical behaviour in simulation; and since they are synthesisable,
you would expect identical results in synthesis too.

In the jargon,
a <= b and c;
is a "concurrent signal assignment".

Note that the rough equivalent in Verilog,
assign a = b & c;
vs
always @(b or c) a = b & c;
are not identical.

Note, too, that the following PAIR of concurrent assignments:

a <= b and c;
d <= e and f;

is not exactly the same as the following SINGLE process:

process (b,c,e,f)
begin
a <= b and c;
d <= e and f;
end process;

(although in practice they would probably give the same results) because the pair of concurrent assignments is equivalent to two separate processes each with its own sensitivity list.Of course, there are lots of stylistic arguments about which formulation is preferable in any given situation.