Need help in writing driver for an add on card with a PCI bridge

How do i write windows device driver for an add on card with a PCI bridge

If you want to write a device driver for windows, one needs the device driver development kit (ddk) and a c compiler. According to this article - http://msdn.microsoft.com/msdnmag/is...l/default.aspx, a device driver's maximum size is 960MB on Windows XP (100MB on NT4, 220MB on Win2K).

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Thank you very much James for your reply.
I have base knowledge in development of SCSI miniport device drivers in windows.
Now i want to develop a driver for an add on card that has a PCI to PCI bridge with almost 8 other PCI devices connected to it .
Do you have any idea of this ?
Should i develop a multifunction PCI driver ?
But my doubt is the 8 devices are not functions in PCI terms . They are also PCI devices. Can you help with this ?

For this I will recommend you to use DriverWizard. It is a diagnostic tool based on windows which will search for pnp devices in your system and specify their hardware configuration. It is possible then to read and write the drivers from that. You can then being writing the driver code form here and test the same. Try this tool might help you work on multi functional support.

Thanks Leonard.
I read in a microsoft whitepaper that " a single PCI device can have multiple memory and I/O ranges." My PCI device also needs 2 memory range as it has 2 BARs in the configuration space. The first BAR specifies some memory requirement and the second BAR represents some other memory requrement.
But from PCI bus driver/ HAL i will get only one memory start address , length through the CM_PARTIAL_RESOURCE_DESCRIPTOR (u.memory.start and length ).How do I get the memory pointer or the physical address for the other BAR ?
Thanks
Rexlin

to get the address the pointer is pointing to:

char ptr[] = "test";

printf("address = %p", ptr);

to get it as a value:

size_t address = (size_t)ptr;

If the PCI device has implemented 2 Base Address registers to indicate that it need to map both its 1. registers and 2. some other memory into the system address space , is it possible ? If the windows os has alloted 2 memory chunks , will the driver receive the memory resource through a list of 2 cm_partial_resource_Descriptors ?
Please anyone who have idea on this , reply to this thread .

The CM_FULL_RESOURCE_DESCRIPTOR structure that serves as the header for the first full resource descriptor. If the CM_RESOURCE_LIST structure contains more than one full resource descriptor, the second full resource descriptor immediately follows the first in memory, and so on. The size of each full resource descriptor depends on the length of the CM_PARTIAL_RESOURCE_DESCRIPTOR array that it contains.

But in Windows ddk , it is given that for CM_RESOURCE_LIST , the count value is always 1. Then how it is possible to have more than 1 full resource descriptor .
In the sample code given below , the for loop is looped with the count associated with the partial resource descriptor's count as the loop count variable . Little confusing .. Can you please clarify ? Thank you very much !


stack = IoGetCurrentIrpStackLocation (Irp);

// Parameters.StartDevice.AllocatedResourcesTranslated points
// to a CM_RESOURCE_LIST describing the hardware resources that
// the PnP Manager assigned to the device. This list contains
// the resources in translated form. Use the translated resources
// to connect the interrupt vector, map I/O space, and map memory.
//

partialResourceListTranslated = &stack->Parameters.StartDevice.\
AllocatedResourcesTranslated->List[0].PartialResourceList;

resourceTrans = &partialResourceListTranslated->PartialDescriptors[0];

for (i = 0;
i < partialResourceListTranslated->Count;
i++, resourceTrans++) {

switch (resourceTrans->Type) {

case CmResourceTypePort:
//
// We will increment the BAR count only for valid resources. We will
// not count the private device types added by the PCI bus driver.
//
numberOfBARs++;

DebugPrint(LOUD, DBG_INIT,
"I/O mapped CSR: (%x) Length: (%d)\n",
resourceTrans->u.Port.Start.LowPart,
resourceTrans->u.Port.Length);

//
// Since we know the resources are listed in the same order the as
// BARs in the config space, this should be the second one.
//
if(numberOfBARs != 2) {
DebugPrint(ERROR, DBG_INIT, "I/O mapped CSR is not in the right order\n");
status = STATUS_DEVICE_CONFIGURATION_ERROR;
goto End;
}

//
// The port is in memory space on this machine.
// We shuld use READ_PORT_Xxx, and WRITE_PORT_Xxx routines
// to read or write to the port.
//

FdoData->IoBaseAddress = ULongToPtr(resourceTrans->u.Port.Start.LowPart);
FdoData->IoRange = resourceTrans->u.Port.Length;
//
// Since all our accesses are USHORT wide, we will create an accessor
// table just for these two functions.
//
FdoData->ReadPort = NICReadPortUShort;
FdoData->WritePort = NICWritePortUShort;

bResPort = TRUE;
FdoData->MappedPorts = FALSE;
break;

case CmResourceTypeMemory:

numberOfBARs++;

if(numberOfBARs == 1) {
DebugPrint(LOUD, DBG_INIT, "Memory mapped CSR:(%x:%x) Length:(%d)\n",
resourceTrans->u.Memory.Start.LowPart,
resourceTrans->u.Memory.Start.HighPart,
resourceTrans->u.Memory.Length);
//
// Our CSR memory space should be 0x1000 in size.
//
ASSERT(resourceTrans->u.Memory.Length == 0x1000);
FdoData->MemPhysAddress = resourceTrans->u.Memory.Start;
FdoData->CSRAddress = MmMapIoSpace(
resourceTrans->u.Memory.Start,
NIC_MAP_IOSPACE_LENGTH,
MmNonCached);
if(FdoData->CSRAddress == NULL) {
DebugPrint(ERROR, DBG_INIT, "MmMapIoSpace failed\n");
status = STATUS_INSUFFICIENT_RESOURCES;
goto End;
}
DebugPrint(LOUD, DBG_INIT, "CSRAddress=%p\n", FdoData->CSRAddress);

bResMemory = TRUE;

} else if(numberOfBARs == 2){

DebugPrint(LOUD, DBG_INIT,
"I/O mapped CSR in Memory Space: (%x) Length: (%d)\n",
resourceTrans->u.Memory.Start.LowPart,
resourceTrans->u.Memory.Length);
//
// The port is in memory space on this machine.
// We should call MmMapIoSpace to map the physical to virtual
// address, and also use the READ/WRITE_REGISTER_xxx function
// to read or write to the port.
//

FdoData->IoBaseAddress = MmMapIoSpace(
resourceTrans->u.Memory.Start,
resourceTrans->u.Memory.Length,
MmNonCached);
if(FdoData->IoBaseAddress == NULL) {
DebugPrint(ERROR, DBG_INIT, "MmMapIoSpace failed\n");
status = STATUS_INSUFFICIENT_RESOURCES;
goto End;
}

FdoData->ReadPort = NICReadRegisterUShort;
FdoData->WritePort = NICWriteRegisterUShort;
FdoData->MappedPorts = TRUE;
bResPort = TRUE;

} else if(numberOfBARs == 3){

DebugPrint(LOUD, DBG_INIT, "Flash memory:(%x:%x) Length:(%d)\n",
resourceTrans->u.Memory.Start.LowPart,
resourceTrans->u.Memory.Start.HighPart,
resourceTrans->u.Memory.Length);
//
// Our flash memory should be 1MB in size. Since we don't
// access the memory, let us not bother mapping it.
//
} else {
DebugPrint(ERROR, DBG_INIT,
"Memory Resources are not in the right order\n");
status = STATUS_DEVICE_CONFIGURATION_ERROR;
goto End;
}

break;

case CmResourceTypeInterrupt:

ASSERT(!bResInterrupt);

bResInterrupt = TRUE;
//
// Save all the interrupt specific information in the device
// extension because we will need it to disconnect and connect the
// interrupt later on during power suspend and resume.
//
FdoData->InterruptLevel = (UCHAR)resourceTrans->u.Interrupt.Level;
FdoData->InterruptVector = resourceTrans->u.Interrupt.Vector;
FdoData->InterruptAffinity = resourceTrans->u.Interrupt.Affinity;

if (resourceTrans->Flags & CM_RESOURCE_INTERRUPT_LATCHED) {

FdoData->InterruptMode = Latched;

} else {

FdoData->InterruptMode = LevelSensitive;
}

//
// Because this is a PCI device, we KNOW it must be
// a LevelSensitive Interrupt.
//

ASSERT(FdoData->InterruptMode == LevelSensitive);

DebugPrint(LOUD, DBG_INIT,
"Interrupt level: 0x%0x, Vector: 0x%0x, Affinity: 0x%x\n",
FdoData->InterruptLevel,
FdoData->InterruptVector,
(UINT)FdoData->InterruptAffinity); // casting is done to keep WPP happy
break;

default:
//
// This could be device-private type added by the PCI bus driver. We
// shouldn't filter this or change the information contained in it.
//
DebugPrint(LOUD, DBG_INIT, "Unhandled resource type (0x%x)\n",
resourceTrans->Type);
break;

}
}

Hi
I am new to wdf and kmdf.
I have coded a device driver for my PCI device.
I have to run this driver in a machine which has Windows 7 OS and Intel dual core processor. For the inf, I have edited the sample pcidrv inf . So what all i have now is the driver.sys,driver.pdf,driverinf.inf.
I have many questions on the installation of the driver and testing .
1. Which build environment should I use ? x86 or x64 or ia64 ?
2. Do i need to have info about coinstaller dll in the inf file ? why do i need a coinstaller ?
3. using the new hardware wizard , when i tried to install the driver , i get a message, "Windows found the hardware for your device. But it is not intended for your platform". Is this error related to the driver or the inf file . I tried building the driver for all the above mentioned build environments .But the error remains the same .

Please help me , if any of you have idea abt this .
thanks
Rexlin