CPU Gflop Performance Database

[Wahab4]

I need, as part of my job, knowing the powers of some of some PC CPUs.So I am looking for some specific software for the same which can help me to calculate the indices of performances.I know that FLOPS is the number of floating-point calculations per second. But in order to see the performance of each and every processor I need such tool that can help me to calculate the number of GFlops.I also need to choose some cpu from the newest one available in the market.

[Deepest BLUE]

The choice of the central elements, processor, motherboard and memory, is now so great that the layman is quickly overwhelmed. For processors, it Athlon XP, Athlon 64, Athlon FX 64, the Duron, Opteron, Pentium 4, Pentium M, Celeron, Xeon, Itanium. For the GLOPS you might need to check for the different types of processor and a comparison list below can help.
Glops Intel

[desilva]

In comparison to a single clock can indeed handle the EUs three SSE instructions. This works but not consistently. This limits the front end or the read rates of the cache. Therefore, an average of SSE instructions per clock cycle. What is just for the i7 980X 83.2 GFLOPS. If I am mistaken, can theoretically three SSE instructions are given simultaneously to the execution units

[Common]

Cache time is excluded (relevant to the theoretical peak FLOPS is not so, because we start from the best case) would then three instructions per clock possible or what fails. Since you apparently do not understand how to calculate theoretical throughput. And after, so expect the hardware theory. And this is an SSE instruction per clock cycle. And the P4 could not handle more than one SSE instructions per clock cycle.

[Abbie]

With the P4 you actually get 2.5 IPC, with a tool called P4 Max Perf simple SSE instructions were used. Theoretically, the P4 with 4 SP operands work per clock (1 MUL, 1 ADD, each have two operands). Single Cycle means only that the execution latency of an instruction is only one measure. About the parallelism tells us nothing. Have now researched a little bit. Whom do we start from x87 is a FLOP per core and clock correctly. If there are two DP SSE operands per instruction x 3 surgeries per Cycle x 6 x 3.33 Ghz cores.

[Omari]

With the new 256-bit extensions that should come with bulldozers and Sandy Bridge, the theoretical throughput is doubled again. Although this is admittedly considered very idealistic but if we compare with the equally unattainable GFLOPS an AMD graphics card, one can see that already so. Even if the data is always from the L1 would get 2 FLOPS per clock would be possible, as you can handle with SSE 2 FP data sets with an instruction.

[JAMES_911]

If you would like to consider the practical, then the manufacturer mentioned theoretical GFLOPs a graphics card are even more unrealistic.You can still only 16 bytes (128-bit read) per cycle from the L1D. For two operations but you would need 2x 128-bit (32 byte). This is an operation per instruction expected. IMD M has only existed since SSE5 or AVX in the x86 ISA.