Core and Cache within Sandy Bridge

[MegaZone]

I am doing the hardware and networking course, and I am interested in chip level of hardware. I am here to know more about the popular Sandy Bridge. As I have found some threads related with the core information of Intel processor, I am sure that you people will explain me about the core and cache present in sandy bridge.

[spuff]

From a distance the day Sandy Bridge looks completely different from that of its predecessor. After all, mid-range CPU Clarkdale consists of two physical chip - a dual-core product and a 32-nanometer graphics core / memory controller integrated controller / PCI Express made at 45 nanometers. We now have a single solution to 32 nanometers with all the skills described in a single piece of silicon. In detail there are several similarities with the older generation that reveal an "evolutionary" nature of this chip.

For each piece of Sandy Bridge observed that, remember one word: integration. Intel wanted to get the most out of each transistor (one billion) of the new architecture (the official number is 995 million).

[VinFanatic]

There are currently three different versions of the day Sandy Bridge. The quad-core processors with integrated graphics - that made 995 million transistors - which measures 216 mm square. Then there is a dual-core die with 12 execution units that make up the graphics core. This design has 624 million transistors on a die of 149 mm square. Finally, the minor variant has two cores and a graphics core with six execution units. Although the transistors are 504 million of that variant, the die size is only 131 mm square.

In comparison, the Lynnfield 45-nanometer design that is the basis of the Core i7 800 and Core i5 700 occupied an area of 296 square millimeters, despite the fact it was composed of only 774 million transistors. Intel's engineers were able to put so many units in Sandy Bridge owe much to those who brought the 32-nanometer production process with solutions Westmere (tick), and then they optimized for these solutions (tock ).

[Zeverto]

At present, the Sandy Bridge processors are obtainable with four cores (with and without Hyper-Threading) and two cores (dual-core models all have the Hyper-Threading enabled). As you will see in the benchmarks, these are core, clock for clock, more influential than those we have seen with the Nehalem devise. There are still the L1 instruction and data cache of 32 KB, although now Sandy Bridge integrates what Intel calls Istruction L0 cache, which contains up to 1500 micro-ops decoded. This feature has the dual effect of saving energy and improving the instruction throughput. If your hardware is fetch the instructions it needs in the cache, the decoder can be switched off until it will again be needed. Intel has also redesigned the branch prediction unit of the Sandy Bridge, improving accuracy. Processors based on Sandy Bridge are the first to support the Advanced Vector Extensions (AVX), a set of extensions to the SSE 256-bit (AMD will support the future architecture of AVX Bulldozer). The emphasis that surrounds AVX comes from the high-performance computing (HPC), where the applications that make intensive floating point computations require more power than ever. From this point of view of the impact on Sandy Bridge AVX will probably be very limited.

[Wannabe]

The emphasis that surrounds AVX comes from the high-performance computing (HPC), where the applications that make intensive floating point computations require more power than ever. From this point of view of the impact on Sandy Bridge AVX will probably be very limited.

However, Intel thinks that the audio and video editing applications should be optimized to take advantage of AVX (together with those for the analysis of financial services and software design / production that is really designed AVX). Of course, to enable AVX has done much work on implementation, including the transition from retirement to a log file to a physical register. This allows operands to be stored in log files, instead of traveling with the micro-ops through the engine out of order. Intel has used the savings in energy and physical space allowed by the registry to increase significantly the size of the buffer, thus serving in a more efficient engine in floating point.

[LasitMalinga]

The highest level of integration has led Intel to deal with the manner in which bits and pieces of your processor accesses the Last Level Cache (LLC, which is the third level of L3 cache). With regard to the design Bloomfield, Lynnfield and Clarkdale, a limit of four core (and even in the case of six-core Westmere) meant that each could have its core physical connection to the shared cache. The Xeon 7500 series processors are designed to be more scalable and models on the market have up to eight cores per CPU. Building them in the same way would lead to the need to implement a huge number of channels of communication between each core and the Last Level Cache. Intel has thus adopted a ring bus that, in enterprise environments, enabling the company to continue to climb number of cores without losing control of the intercom system. Intel was not worried by the largest number of cores on the mainstream desktop variant of Sandy Bridge. Rather it was the integrated graphics on the day that forced the adoption ring bus architecture, which now connects graphics, up to four cores, and the party system agent (formerly uncore). The latency is variable, since each component takes the shortest path on the bus, even if it is always lower than that of a processor Westmere.