AMD Opteron 6174 with 12 cores

[iucliPse]

I know that AMD has introduced new Opteron 6100-series its next generation of server CPUs. With 12 cores, four DDR3 memory channels and Direct Connect Architecture 2.0 is challenged Intel's Xeon 5600-series again. In the test, convinced the model Opteron 6174 with high efficiency. But I am looking for more information about it. I want to know more about architecture. The balance of power between AMD and Intel for servers with two processors was to be clearly established. Intel's mid-March 2010 featured 6-core CPUs of Intel Xeon 5600 series lead the rankings in both the performance and energy efficiency over the Opteron 2400 models to clear. But what about the performance and other things of it. I hope that some members having knowledge about Opteron 6100 series would be interested in helping me.

[Mentos]

Despite the same number of cores are Intel's 32nm Xeons with clock frequencies up to 3.33 GHz, Hyper-Threading and three additional DDR3-1333 memory channels per CPU in the clear advantage. AMD is now with the new Opteron 6100-series Magny-Cours for counterstrike. By doubling the 6100 core processors are now working with twelve computer stations. This has the AMD x86 CPUs, which have by far the highest number of cores. Intel's upcoming expected Xeon Nehalem-EX 8-core architecture has a disadvantage - at least in the core number.

[AlienKing]

In addition to pure performance servers also high memory bandwidth are required. Here, too, the Opteron on a lot: Four memory channels for DDR3-1333 DIMMs per CPU care for more than a doubling of bandwidth. The previous models of the Opteron 2400-series are limited to two DDR2-800 channels. The new memory technology with twice the channels the persisted over many years with the Socket F platform stability, however, has had its day. The Opteron 6100 processors take the slot G34 together with the associated new platform place. Here also, AMD Direct Connect Architecture 2.0 in - with faster and extra HyperTransport links. The performance of the CPUs in integer and floating point applications as well as encryption, rendering and simulation. The speed of Java applications is also investigated how the energy efficiency of the two-socket systems.

[Shutdown]

AMD built the 12-core Opteron processor 6100 - code for two silicon chips in a CPU . This puts AMD at a distinct advantage of always declared native multi-core design. Intel used this method recently at the Quad-Core CPUs of Xeon 5400 series . The two 6-core of this is in each case - as with the Opteron 2400 Istanbul - 6 MB of L3 cache. Overall, the 12-core processor has with its multi-chip design therefore has 12 MB L3 cache. Unchanged, each core has a dedicated 512 KB L2 cache-making. AMD Opteron 6100 for positioning the server with two and four-socket, the performance per watt and expandability are designed on high. There is thus no longer 2000 series for 2-socket systems and a 8000 series for servers with four or eight processors (the Socket-F CPU time being remain in the program). The production, will continue with AMD's 45 nm technology. The Opteron 6100 is largely unchanged on the K10 architecture of current AMD CPUs with 45-nm technology.

[McGrawh]

The Opteron 6100 AMD equips the first time with "Direct Connect Architecture 2.0". This means AMD an integrated 4-channel memory controller for DDR3-1333 DIMMs. Per CPU should thus 12 DIMMs - can be controlled, such as AMD specifies - three per channel. Low-Voltage DDR3 DIMMs at 1066 MHz and 1.35 instead of 1.5 V operating voltage supports the Opteron 6100 as well. AMD stressed that the Opteron 6100 offers even when fully loaded one-DIMM memory speed of 1333 MHz. The Xeon 5600 processors want the third DIMM per channel of 1333 back to 1066 MHz. To increase the memory bandwidth in 4-socket systems, in addition, equipping the AMD Opteron 6100 CPUs with "Direct Connect Architecture 2.0" with four instead of the maximum of three HyperTransport links, Socket-F models. Where four Opterons connected via HyperTransport each other, each CPU, the memory of each adjacent additional access. Instead of 4.8 GT / s works just like the Socket F Opterons due to the Opteron 6100 HyperTransport 3.0, now with a bandwidth of 6.4 GT / s per link ..

[Zeverto]

AMD's Opteron 6100-series is in spite of doubling the core and used 45-nm process technology to remain economical in the use of energy. The manufacturer's 12-core processors gradually with an ACP of a 65, 80 and 105 watts. Its previous Hexa-core models of the Opteron 2400-series AMD, 40, 55, 75 and also 105 Watts ACP to. Instead of the TDP (Thermal Design Power) used by Intel, a theoretical maximum value, in which all the transistors in the CPU switch simultaneously, AMD used in the classification of the energy value of ACP (Average CPU Power). These are, according to the manufacturer to a realistic maximum value. The ACP is located below each of the TDP-value that there are still developers. New for the Opteron 6100 is the power saver C1e. If all processors in idle mode (C1-status) and AMD's Smart Fetch technology , the L1 cache and L2 cache contents in the L3-loaded (nuclei are then turned off), then the C1E active sleep mode.

[Alchmey]

New for the Opteron 6100 is the power saver C1e. If all processors in idle mode (C1-status) and AMD's Smart Fetch technology , the L1 cache and L2 cache contents in the L3-loaded (nuclei are then turned off), then the C1E active sleep mode.

C1e reduced from the L3 cache and the memory controller's speed and HyperTransport links can go into a sleep mode LS2. In addition, turned off the DRAM DLLs and the chipset can be reduced by the fashion of the LS2-HT also links its energy consumption. According to AMD Opteron reduce two 6100 in a 2-socket system by C1e mode its power consumption by a total of about 34 watts. In addition to the known energy-saving measures "PowerNow!" To dynamically adjust the clock frequency and core voltage as well as "Smart Fetch the Opteron 6100 additionally supports the technology," Cool Speed ". AMD's Cool Speed reduces the P-states (operating state with defined clock frequency and core voltage) when a temperature limit is reached. Thus, the reliability is increased.