Inclusion Property in Multilevel Caches

[Charioteer]

I am currently operating on inclusion property in multilevel of cache system; I want to know that in Multi-core architecture of Intel, does Intel ensure inclusion property at every level of cache coherency? And also there are two techniques snooping and invalidation for ensuring cache coherency, which of the one does Intel processors use?

[Amd Athlon]

I have gone through question, from that I come to know is that there are many examples of these two techniques. There are quite entire topic is covered on the cache coherency, some points to the invalidation and some points to snooping that Intel use for cache coherency. But I think snooping technique uses by Intel for cache coherency.

[PeterAGASSI]

As far I have receive information that is, it does ensure inclusion property at every level of cache coherency. Cache line up lives on cores either on L1 or L2, it is set in L3 as well, which aids to decrease snoop traffics. If other processor is writing to the memory then L3 is not take part in operating snooping. And it does not lie in cores that time.

[Joshua]

Both invalidating and snooping are the solution for cache coherency but in invalidating there is duplicate lines in one of the lines when the line is modified. And hardware not use any software interference to invalidate it does it by using snooping logic. We cannot exactly predict which is the technique is perfect for cache coherency.

[Russell]

I think snooping is the technology which is use by Intel for cache coherency. I have read it about snooping, which is use to determine cache stability. This is transmitting over the bus also snoops bus looking for such messages generated by processors. I think this information may really put knowledge on your question.