Controller for DDR2 interface issue

[wirelessprom]

I'm running Windows Xp as my operating system. I don't have much detail information on DDR2. So, I would like to know where can i get a sample controller that can control the interface with DDR2. Can anyone tell me that where can i get Controller for DDR2 interface? Any one knows about it? Kindly provide me the correct information on the above issue. Thanks.

[Amd Athlon]

In the old legacy ddr2 controller, user need to specify more timing information in the settings window. I think you're only hurdle here is becoming familiar with everything. As such, I'd start with the NIOS and DDR2 controller and start playing around with that. But the new DDR2 core use the training sequence to adjust the timing automatically by reading and writing to the first few bytes in the memory.

[PeterAGASSI]

If you have a Quartus II subscription license, you can use the included IP instead of writing your own. Then add a DMA controller and maybe some useless peripheral (like a gpio port) and try streaming data from the gpio port. DDR2 SDRAM High-Performance Controller is recommended for most designs for higher overall performance and easier timing closure; DDR2 SDRAM Controller is available for designs that need lower latency.

[Joshua]

A typical DDR2 memory subsystem uses a DIMM to house multiple DDR2 memory devices. In the old legacy ddr2 controller, user need to specify more timing information in the settings window, but the new DDR2 core use the training sequence to adjust the timing automatically by reading and writing to the first few bytes in the memory. The emerging DDR3 memory standard will extend the performance range of DDR memories considerably, while maintaining some amount of backwards compatibility with the existing DDR2 memory standard.

[Russell]

The DDR2 memory standard is being upgraded with the advent of the DDR3 standard. The Memory Controller family represents full-featured, general-purpose memory controllers which convert host port memory requests into DDR transactions and include support for up to 32 host ports, flexible port arbitration, and advanced command reordering/scheduling to optimize DDR data bus utilization.

[MattyBoy]

The scheduler prioritizes the current list of commands and determines which command is the most urgent and issues that command to the DRAM. The Protocol Controller family offer a low-latency, high performance single port controller which converts host port memory requests into DDR transactions and is ideally suited to accommodate custom-designed memory management units.