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Thread: Data Transmits between the CPU and L2 Cache over what

  1. #1
    Join Date
    Aug 2009
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    Data Transmits between the CPU and L2 Cache over what

    I am learning computer engineering & and i came across a question is that What is L2 Cache...??? & Over what is the Data transmitted between CPU & L2 Cache??? Please Help...???

  2. #2
    Join Date
    Jan 2009
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    126

    Re: Data Transmits between the CPU and L2 Cache over what

    Normally a two-level cache is a processor chache, in which level 1 cache (L1) is smaller and faster; while level 2 cache (L2) is slightly slower, but anytime faster than the main memory. The size of the cache line is usually larger than the size of the usual access requested by a CPU instruction, which ranges from 1 to 16 bytes. Each location in each memory also has an index, which is a unique number used to refer to that location. The index for a location in main memory is called an address.L1 cache is divided into two parts , instruction cache and data cache. Instruction cache stores the set of instructions that are required by the CPU for computing; while the data cache stores the values that are required for current execution. L2 cache is responsible for loading the data from the main memory.

  3. #3
    Join Date
    Oct 2005
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    1,217

    Re: Data Transmits between the CPU and L2 Cache over what

    Level Two Cache is a cache where you CPU stores your daily used programs setting also frequently used program... Data is transmitted from CPU to L2 Cache is Front Sidebus.

  4. #4
    Join Date
    Sep 2005
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    1,434

    Re: Data Transmits between the CPU and L2 Cache over what

    L3 cache multi-Core has entered the way with the coming up CPU. Considering that these Chips will have both separately caches L1 and L2 for each nucleus, there is one quite great common L3 shared by all the nucleus. Generally, the size of all the you break of others combined or a multiple of all the hiding places of combining. Also it is applied in the DRAM. An unusual thing is that a chip multi-Core who is executing a software that can not be able of necessity or of all the nuclei it will have a nucleus of color of his hiding places in the L3 before the nucleus follows latent.

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